Pass the ARM AAE EN0-001 Questions and answers with ExamsMirror

It must start executing from RAM

RAM must be initialized before reset

Exception handlers must execute from ROM or flash memory

It must not execute semihosting SVC or BKPT instructions

SWP, SWPB

TEQ, TST

STC, SBC

LDREX, STREX

The exception vector table

The Memory Management Unit (MMU) translation table

The Stack Pointer (SP)

The System Control Register (SCTLR)

Processor reset

Switching from ARM to Thumb state

Changing the access permissions of a page

Executing a Data Memory Barrier instruction

Loading data from an unaligned memory address

Produce an image which is decompressed at run-time.

Cause the compiler to unroll loops where possible.

Result in more functions being inlined by the compiler.

Produce smaller code, even if this results in slower execution.

In a multi-threaded system, when two threads need to be synchronized at a particular point

When accessing a peripheral, it is necessary to halt until the memory access is complete

When it is necessary to temporarily disable interrupts while carrying out a particular memory access

In a multiprocessor system, when it is necessary to halt one of the cores while the other completes a critical task

Supervisor Call

FIQ

Undefined Instruction

Parity

The memory contents could be set to zero

Some memory contents could be rewritten

The processor MMU pagetables could be modified

The processor cache could be cleaned or/and invalidated

Influenced by breakpoints.

Intrusive on normal processor operation.

Inaccurate regarding code execution history.

Not intrusive on normal processor operation.

They can contain unresolved relocations

They contain the code and data for all libraries they use

They are larger than an equivalent statically linked application

They are designed to be run standalone with no other supporting software